A. Field of the Invention
The present invention relates to semiconductor devices such as power MOS devices used in electrical power converters. Specifically, the present invention relates to reverse blocking semiconductor devices exhibiting breakdown voltage characteristics (symmetrical or asymmetrical) including a forward breakdown voltage and a reverse breakdown voltage. The present invention relates also to the two-way switching devices using the reverse blocking semiconductor devices.
B. Description of the Related Art
VVVF inverters capable of varying the frequency and the voltage thereof are used very often to drive motors and such machines. Usually, the VVVF inverter includes a converter section, which converts an AC having a commercial frequency to a DC, and an inverter section, which converts the converted DC to an AC having a predetermined frequency and a predetermined voltage.
When it is desired to use the VVVF inverter as an electric power converter, it is necessary to provide the electric power converter with a converter section, an inverter section, a large inductor for smoothing the current, and a large capacitor for suppressing the voltage variations. Therefore, the size of an electric power converter necessarily is large. From the view point of obtaining a small and very efficient electric power converter, a matrix converter, which converters an AC not to a DC but directly to another AC, has been attracting increased attention.
FIG. 31(a) is a circuit diagram of a matrix converter. FIG. 31(b) is a diagram of a two-way switch circuit including conventional two-way switching devices. To configure this matrix converter, two-way switching devices, which can switch at a high frequency, are indispensable. When a reverse blocking IGBT (insulated gate bipolar transistor) is not available, a two-way switching device is manufactured by connecting a series circuit consisting of a conventional IGBT 51 and a diode 53 for reverse blocking and a series circuit consisting of a conventional IGBT 52 and a diode 54 for reverse blocking in opposite parallel.
However, the on-voltage of the two-way switching device, which is the sum of the on-voltages of the diodes 53, 54 and the IGBT's 51, 52, is inevitably high. Therefore, for obtaining a two-way switching device exhibiting high performance, a reverse blocking IGBT exhibiting high performances is indispensable.
FIG. 32(a) is a top plan view of a conventional reverse blocking IGBT. FIG. 32(b) is a cross sectional view of the conventional reverse blocking IGBT along the line segment X—X of FIG. 32(a). Referring now to these figures, the conventional reverse blocking IGBT includes an n−type drift region 1 as a semiconductor substrate 100. Cells are in the surface portion of n−-type drift region 1. Each cell includes a p-type base region 3. In the surface portion of p-type base region 3, n+-type emitter regions 6 and 6 are formed. A gate electrode 8 is above the extended portion of p-type base region 3 that extends between n+-type emitter region 6 and n−-type drift region 1, with a gate insulation film 7 interposed between gate electrode 8 and the extended portion of p-type base region 3. An emitter electrode 10 is in contact with p-type base regions 3 and n+-type emitter regions 6 through holes 12. An interlayer insulation film 9 insulates gate electrode 8 and emitter electrode 10 from each other. A p+-type collector region 15 is on the back surface of n−-type drift region 1. A p-type separation region 2 is in contact with p+-type collector region 15 and the side faces of n−type drift region 1. A collector electrode 16 is on p+-type collector region 15. In the reverse blocking IGBT of FIGS. 32(a) and 32(b), the surface portion of n−-type drift region 1 between the adjacent cells is covered with gate insulation film 7 and isolated electrically from emitter electrode 10.
Japanese Unexamined Laid Open Patent Application 2003-17701 discloses intentional utilization of the parasitic diode in a trench MOSFET for a free wheel diode. In the trench gate MOSFET, each cell includes a base region sandwiched between the trenches and isolated from the base regions in the other cells such that a drift region is exposed. A Schottky junction is formed between the exposed portion of the drift region and a part of the emitter electrode. A high current is made to flow through the Schottky diode including the Schottky junction such that the Schottky diode is utilized for a free wheel diode. The on-voltage of the Schottky diode is lower than the on-voltage of the diode including a pn-junction between the base region and the drift region thereof, since the threshold voltage (Schottky barrier) of the Schottky junction is lower than the threshold voltage (built-in voltage) of the pn-diode. Thus, down-sizing of the semiconductor device is realized by forming a Schottky junction on the exposed portion of the drift region. This structure is applied also to an IGBT.
Japanese Unexamined Laid Open Patent Application 2002-76017 reports utilization of a reverse blocking IGBT as a diode. In the utilization, a positive gate voltage is applied to open channels such that the collector of the reverse blocking IGBT is used for the anode of the diode and the emitter of the reverse blocking IGBT for the cathode of the diode. This document describes reduction of the peak reverse recovery current in the reverse blocking IGBT used in the diode mode by introducing a lifetime killer to the drift region for obtaining soft recovery characteristics.
Japanese Unexamined Laid Open Patent Application 2002-319676 describes lowering of the on-voltage in the IGBT mode of operation, reduction of the reverse recovery current in the diode mode of operation, and realization of soft recovery characteristics in the diode mode of operation by reducing the thickness of the collector region of a reverse blocking IGBT down to around 1 μm.
Japanese Unexamined Laid Open Patent Application 2001-185727 describes a reverse blocking IGBT provided with a positive bevel structure for obtaining a certain forward breakdown voltage and a certain reverse breakdown voltage.
FIG. 33 is a cross sectional view of a conventional reverse blocking IGBT describing the biased state thereof. When a reverse bias voltage is applied between the emitter and the collector, the electrons generated in the depletion layer are injected into p-type base regions 3 working as channels, and into a p-type region 4 in the periphery of the active region. Holes are injected from emitter regions 6 such that the electrons injected into p-type base regions 3 are neutralized. The number of the electrons generated in the depletion layer keeps increasing. When a reverse bias voltage is applied to a reverse blocking IGBT, a depletion layer expands from the back surface side. Therefore, the number of electrons generated in the depletion layer expanding from the back surface side increases. Due to the increase of electrons in the depletion layer, a large reverse leakage current flows when a reverse bias voltage is applied (in the reverse blocking state).
The reasons why the number of the electrons generated in the depletion layer increases and the reverse leakage current increases are as follows. First, defects are left in p+-type collector region 15 formed in the back surface portion of the reverse blocking IGBT by low temperature annealing. When a reverse bias voltage is applied, a depletion layer expands from the pn-junction in the back surface portion of the IGBT into p+-type collector region 15. In other words, a high-electric-field region is created in p+-type collector region 15. Since p+-type collector region 15 is formed by annealing at a low temperature between 300 and 500°, crystal defects are left in p+-type collector region 15. The time for which carriers are generated through the defects (the carrier generation lifetime) is very short. In other words, carriers are generated very frequently. The carriers generated in p+-type collector region 15 are made to migrate by the electric field, causing a leakage current.
Second, the generated carriers described above (electrons) are amplified by parasitic transistors in the IGBT. The parasitic transistors include a pnp-transistor formed of p-type base region 3, n−-type drift region 1, and p+-type collector region 15, and a pnp-transistor formed of p-type regions 4 and 5, n−-type drift region 1, and p+-type collector region 15. In the forward blocking state of the IGBT, p-type region 4 is not effective to reduce the forward leakage current. In the turning off of the IGBT, p-type region 4 extracts the holes accumulated in n−-type drift region 1, resulting in an excellent turning off performance of the IGBT.
The p-type diffusion regions in the surface portion of the IGBT, such as p-type base regions 3, p-type region 4 and p-type region 5, are doped heavily to secure an appropriate MOS threshold voltage and to avoid latching up. In the surface portions of these p-type diffusion regions, the dopant concentration is higher than 1×1019 cm−3. Due to the high surface dopant concentration, the emitter injection efficiencies (the efficiencies of injection from the p-type diffusion regions to the n-type drift region across the pn-junctions between the p-type diffusion regions and the n-type drift region) of the parasitic pnp-transistors are extremely high and the amplification factors thereof are large. Due to the large amplification factors, the electron current generated in the back surface portion of the IGBT is amplified, causing a high leakage current.
In a conventional reverse blocking IGBT, the emitter and the n−-type drift region (that is the bases of the parasitic transistors) are connected electrically to each other via MOS channels when a positive bias voltage is applied between the gate and the emitter thereof. Therefore, the electrons generated in the back surface portion of the conventional reverse blocking IGBT flow to the emitter electrode through the channels without entering the p-type diffusion regions in the surface portion of the IGBT. Thus, the electron current is not amplified and the reverse leakage current is reduced dramatically. However, it is very complicated and difficult for the circuit, to which the matrix converter as shown in FIG. 31(a) is applied, to detect the reverse blocking IGBT biased at a reverse bias potential and to apply a positive voltage to the gate thereof.
The above described problem may be avoided by setting the voltage between the gate and the emitter at 0 V to bias the reverse blocking IGBT at a reverse bias potential. When the voltage between the gate and the emitter of the reverse blocking IGBT is set at 0 V to bias the IGBT at a reverse bias potential, a depletion layer expands from the pn-junction between p+-type collector region 15 in the back surface portion of the IGBT and n−-type drift region 1 into n−-type drift region 1 and toward p-type base regions 3. During this process, electrons flow into p-type base regions 3 from a region, in which charge neutrality is retained (hereinafter referred to as a “charge-neutrality region”), left undepleted in n−-type drift region 1 on the side of p-type base regions 3. In response to this, holes flow into n−-type drift region 1 from p-type base regions 3, making the pnp transistor work.
Since a heavily doped p+-type region is formed in p-type base region 3, a very high emitter injection efficiency of 0.8 or higher is caused in a conventional reverse blocking IGBT, further causing a high current amplification factor α pnp. Due to the high current amplification factor, an extremely high leakage current of 10 mA/cm2 or higher is caused at a high temperature of 100° or higher when the reverse blocking IGBT is biased at a reverse bias potential.
Transport efficiency can be reduced in order to reduce the amplification factor of the parasitic bipolar transistor. The transport efficiency is reduced by shortening the recombination lifetime in n−-type drift region 1, for example, by introducing crystal defects by electron beam irradiation and similar methods. As the amplification factor is reduced, the leakage current is also reduced. However, since the crystal defects introduced shorten the carrier generation lifetime, a large forward leakage current is caused. When the dose amount of electron beam is too large, a higher steady state on-voltage is caused, causing additional large losses.
As described in Japanese Unexamined Laid Open Patent Application 2003-17701, a Schottky junction is formed in a MOSFET to use the Schottky diode for a free wheel diode. This makes it unnecessary to additionally mount an individual free wheel diode by using the Schottky diode for a free wheel diode, and chip size is reduced. This document also intends to reduce loses by using the Schottky diode for a free wheel diode. Therefore, the Schottky junction is formed in the entire exposed surface area of the drift region. Formation of the Schottky junction in the entire exposed surface area of the drift region in the MOSFET is preferable to reduce the on-voltage of the Schottky diode used for the free wheel diode.
Although the embodiment of an IGBT which utilizes a Schottky diode for a free wheel diode is described in Japanese Unexamined Laid Open Patent Application 2003-17701, the effects thereof are not described. The simulations conducted by the present inventors have revealed that an electron accumulation layer will not be formed in the surface portion of the drift region if a Schottky junction is formed in the entire exposed surface area of the drift region in the IGBT. Therefore, electron concentration in the surface portion of the drift region is lowered, the electrical resistance of the drift region is increased, and the on-voltage of the IGBT is increased.
In view of the foregoing, it is a first object of the invention to obviate the problems described above. It is a second object of the invention to provide a semiconductor device that facilitates reducing the leakage current caused by reverse bias voltage application and reducing the on-voltage of the IGBT. It is a third object of the invention to provide the method of manufacturing the semiconductor device. It is a fourth object of the invention to provide the two-way switching device using the semiconductor devices.